TCSESM043F2CS0以太網交換機，SCHNEIDER配置說明
寫入VMEchip2中的LCSR必須為32位。LCSR8位或16位的寫入以TEA信號終止。寫入GCSR可以是8、16或32位。讀取LCSR和GCSR可以是8位、16位或32位。應使用字節讀取來讀取中斷向量。4.該區域不返回確認信號。如果當地總線計時器啟用，訪問超時，并通過以下方式終止茶的信號。5、尺寸為近似值。6.82596CA的端口命令必須寫入兩個16位寫：第一個上單詞，第二個下單詞。
TCSESM043F2CS0以太網交換機7.參考MCchip中的閃存和EPROM接口部分第3章中的說明。詳細的輸入/輸出內存映射表3-3至3-12提供了VMEchip2的詳細內存映射MCchip，Zilog Z85230串行通信控制器，Intel 82596CALAN控制器、NCR 53C710 SCSI控制器、IPIC芯片和MK48T08 BBRAM/TOD時鐘。劃分MK48T08 BBRAM（也稱為非易失性RAM或NVRAM）分為六個區域，如表3-10所示。前五個領域的定義如下：軟件，而第六個區域，即一天中的時間（TOD）時鐘，由芯片硬件。第一個區域是為用戶數據保留的。使用第二個區域摩托羅拉網絡軟件。第三個區域由操作人員使用系統第四個區域由MVME162板調試器使用（MVME162Bug）。第五個區域是配置，詳見表3-11地區第六個區域，即TOD時鐘，詳見表3-12，由芯片硬件。配置字節的數據結構從$FFFC1EF8開始，如下所示跟隨。字段定義如下：1、本結構的修訂或版本保留四個字節。這
版本以ASCII格式存儲，前兩個字節為主要字節版本號，最后兩個字節是次要版本號。例如，如果此結構的版本為1.0，則此字段包含：01002.ASCII中為板的序列號保留了12個字節
總體安排例如，該字段可以包含：0000004704763.ASCII格式的板ID保留了16個字節。例如
對于帶有MC68040、SCSI、以太網、4MB DRAM和512KB SRAM，此字段包含：MVME162-23（10個字符后接6個空格。）4.16個字節用于印刷線路組件（PWA）編號以ASCII格式分配給該電路板。這包括01-W前綴。這如果一個集合需要多個板，則用于主邏輯板。集合中的其他板由該集合的結構定義。對于例如，對于帶有MC68040、SCSI、以太網、4MB的MVME162板
DRAM和512KB SRAM，在版本A中，PWA字段包含：01-W3814B01A（12個字符后接四個空格。）
Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR
writes of 8 or 16 bits terminate with a TEA signal. Writes to the
GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR
may be 8, 16 or 32 bits. Byte reads should be used to read the
interrupt vector.
4. This area does not return an acknowledge signal. If the local
bus timer is enabled, the access times out and is terminated by
a TEA signal.
5. Size is approximate.
6. Port commands to the 82596CA must be written as two 16-bit
writes: upper word first and lower word second.
7. Refer to the Flash and EPROM Interface section in the MCchip
description in Chapter 3.
Detailed I/O Memory Maps
Tables 3-3 through 3-12 provide detailed memory maps for the VMEchip2, the
MCchip, the Zilog Z85230 serial communications controller, the Intel 82596CA
LAN controller, the NCR 53C710 SCSI controller, the IPIC chip, and the
MK48T08 BBRAM/TOD Clock.The MK48T08 BBRAM (also called Non-Volatile RAM or NVRAM) is divided
into six areas as shown in Table 3-10. The first five areas are defined by
software, while the sixth area, the time-of-day (TOD) clock, is defined by the
chip hardware. The first area is reserved for user data. The second area is used
by Motorola networking software. The third area is used by the operating
system. The fourth area is used by the MVME162 board debugger
(MVME162Bug). The fifth area, detailed in Table 3-11, is the configuration
area. The sixth area, the TOD clock, detailed in Table 3-12, is defined by the
chip hardware.
The data structure of the configuration bytes starts at $FFFC1EF8 and is as
follows.The fields are defined as follows:
1. Four bytes are reserved for the revision or version of this structure. This
revision is stored in ASCII format, with the first two bytes being the major
version numbers and the last two bytes being the minor version numbers.
For example, if the version of this structure is 1.0, this field contains:
0100
2. Twelve bytes are reserved for the serial number of the board in ASCII
format. For example, this field could contain:
000000470476
3. Sixteen bytes are reserved for the board ID in ASCII format. For example,
for an MVME162 board with MC68040, SCSI, Ethernet, 4MB DRAM, and
512KB SRAM, this field contains:
MVME162-23 (The 10 characters are followed by six blanks.)
4. Sixteen bytes are reserved for the printed wiring assembly (PWA) number
assigned to this board in ASCII format. This includes the 01-W prefix. This
is for the main logic board if more than one board is required for a set.
Additional boards in a set are defined by a structure for that set. For
example, for an MVME162 board with MC68040, SCSI, Ethernet, 4MB
DRAM, and 512KB SRAM, at revision A, the PWA field contains:
01-W3814B01A (The 12 characters are followed by four blanks.)
