IS220PRTDH1A 363A4940CSP6燃機通用卡件,GE使用數量
軟件可編程硬件中斷8個軟件可編程硬件中斷由VMEchip2。這些中斷允許軟件創建硬件中斷。請參閱MVME162嵌入式控制器中的VMEchip2說明詳細編程信息的程序員參考指南。本地總線超時MVME162在VMEchip2和MCchip中提供超時功能對于本地總線。當計時器啟用且本地總線訪問超時時，傳輸錯誤確認（TEA）信號被發送到本地總線主機。這個超時值可由軟件選擇8微秒、64微秒、256微秒或無限長。
IS220PRTDH1A 363A4940CSP6燃機通用卡件本地總線計時器在VMEbus綁定周期內不工作。VME總線綁定周期由VMEbus訪問計時器和VMEbus全局計時器計時計時器。請參閱MVME162中的VMEchip2和MCchip說明嵌入式控制器程序員詳細編程參考指南信息MCchip還為MVME162提供了本地總線超時邏輯，而無需可選的VMEbus接口（即，沒有VMEchip2）。定時性能本節提供MVME162的性能信息。這個MVME162的設計工作頻率為25 MHz。本地總線到DRAM循環時間DRAM基址、陣列大小和設備大小可編程。這個如果DRAM大小需要八個物理設備（即，當內存陣列大小為4MB時DRAM技術是每個設備4Mbit；或者當內存陣列大小為16MB時DRAM技術是每臺設備16Mbit。）奇偶校驗和奇偶異常操作也可編程。DRAM陣列大小和設備大小在DRAM空間大小寄存器中初始化。TEA是MC68040總線錯誤事務信號。“配茶”指示如果發生DRAM奇偶校驗錯誤，則會發生總線錯誤周期檢測。EPROM/閃存循環時間EPROM/閃存周期時間可在3到10個總線時鐘/字節之間編程（4字節=12到40）。（實際循環時間可能因設備而異速度。）數據傳輸為32位寬。參考MVME162嵌入式控制器程序員參考指南。SCSI傳輸MVME162包括一個與DMA的SCSI大容量存儲總線接口控制器。SCSI DMA控制器使用FIFO緩沖區連接8位SCSI總線到32位本地總線。FIFO緩沖區允許SCSI DMA控制器以四個長字突發有效地將數據傳輸到本地總線。Software-Programmable Hardware Interrupts
Eight software-programmable hardware interrupts are provided by the
VMEchip2. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 desciption in the MVME162 Embedded Controller
Programmer’s Reference Guide for detailed programming information.
Local Bus Timeout
The MVME162 provides timeout functions in the VMEchip2 and the MCchip
for the local bus. When the timer is enabled and a local bus access times out,
a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The
timeout value is selectable by software for 8 μsec, 64 μsec, 256 μsec, or infinity.
The local bus timer does not operate during VMEbus bound cycles. VMEbus
bound cycles are timed by the VMEbus access timer and the VMEbus global
timer. Refer to the VMEchip2 and MCchip descriptions in the MVME162
Embedded Controller Programmer’s Reference Guide for detailed programming
information.
The MCchip also provides local bus timeout logic for MVME162s without the
optional VMEbus interface (i.e., without the VMEchip2).
Timing Performance
This section provides performance information for the MVME162. The
MVME162 is designed to operate at 25 MHz.Local Bus to DRAM Cycle Times
The DRAM base address, array size, and device size are programmable. The
DRAM controller assumes an interleaved architecture if the DRAM size
requires eight physical devices (that is, when memory array size is 4MB and
DRAM technology is 4 Mbits per device; or when memory array size is 16MB
and DRAM technology is 16 Mbits per device.)
Parity checking and parity exception action is also programmable. The DRAM
array size and device size are initialized in the DRAM Space Size Register.
TEA is the MC68040 bus error transaction signal. "With TEA"
indicates that a bus error cycle occurs if a DRAM parity error was
detected.
EPROM/Flash Cycle Times
The EPROM/Flash cycle time is programmable from 3 to 10 bus clocks/byte
(4 bytes = 12 to 40). (The actual cycle time may vary depending on the device
speed.) The data transfers are 32 bits wide. Refer to the MVME162 Embedded
Controller Programmer’s Reference Guide.
SCSI Transfers
The MVME162 includes an SCSI mass storage bus interface with DMA
controller. The SCSI DMA controller uses a FIFO buffer to interface the 8-bit
SCSI bus to the 32-bit local bus. The FIFO buffer allows the SCSI DMA
controller to efficiently transfer data to the local bus in four longword bursts.
