DEIF IOM4.2 2044230041E 2044230040H伺服模塊
WAITRMC控制MVME147的多個解決RMC（MARMC）循環。設置WAITRMC時MVME147在執行之前始終等待VMEbus主控MARMC循環。如果需要，則應設置WAITRMC保證MARMC循環的不可分割性（僅當其他主機以與相同的方式實現MARMC循環MVME147）。當WAITRMC被清除時，MVME147僅等待VMEbus如果MARMC循環開始于VMEbus，則為mastership。
DEIF IOM4.2注意，無論WAITRMC位的狀態如何，如果MVME147在MARMC，它會一直保持到MARMC已完成。只有當VMEchip中的MASWP位時，WAITRMC操作才有效清除LCSR（位5$FFFE2005）（禁用MASWP過帳。）位6-7這些位確定可訪問的本地DRAM部分DMA期間的噴槍。這些位對生成的中斷級別進行編程。0級不會生成中斷。位3當該位為高位時，中斷被啟用。中斷是此位低時禁用。位7當中斷被禁用時，該位為低，為高當中斷被啟用時。這些位表示PCC的修訂級別。初始零件釋放為0級。如果需要在在以后的部分中，修訂級別將增加。這允許如果功能更改PCC中要求。STAT12表示保險絲+12V電源的狀態以太網收發器電源和串口上拉電源。位1低總是0。當打印機忙時，位3 BSY為1，不忙時為0。當打印機處于缺紙狀態時，位4 PE為1；當打印機處于缺紙狀態時，位4 PE為0事實并非如此。選擇打印機時，位5 SELECT為1，未選擇打印機時為0。當打印機處于故障狀態時，位6故障為1，當打印機處于故障狀態時，位6故障為0
不當打印機確認為真時，位7 ACK為1，否則為0。
WAITRMC controls the MVME147 implementation of multiple
address RMC (MARMC) cycles. When WAITRMC is set, the
MVME147 always waits for VMEbus mastership before executing
an MARMC cycle. WAITRMC should be set if it is desired to
guarantee indivisibility of MARMC cycles (only guaranteed if the
other master implements MARMC cycles the same way as the
MVME147).
When WAITRMC is cleared, the MVME147 only waits for VMEbus
mastership if the MARMC cycle starts out by going to the VMEbus.
Note Regardless of the state of the WAITRMC bit, if the
MVME147 obtains VMEbus mastership during an
MARMC, it maintains it until all of the cycles of
the MARMC are completed.
WAITRMC operation is effective only if MASWP bit in the VMEchip
LCSR (bit 5 $FFFE2005) is cleared (MASWP posting is disabled.)
Bits 6-7 These bits determine the section of local DRAM that is accessible to
the LANCE during DMA. These bits program the interrupt level that is generated. Level 0
does not generate an interrupt.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low.
Bit 7 This bit is low when the interrupt is disabled and it is high
when the interrupt is enabled.These bits represent the revision level of the PCC. Initial parts
are released as level 0. If functional changes are required in
future parts, the revision level is incremented. This allows the
software to configure itself should functional changes be
required in the PCC. STAT12 indicates the status of the fused +12V power for
Ethernet transceiver power and for serial port pull up power.
Bit 1 LOW is always 0.
Bit 3 BSY is 1 when the printer is busy and 0 when it is not.
Bit 4 PE is 1 when the printer is in the paper empty state and 0 when
it is not.
Bit 5 SELECT is 1 when the printer is selected and 0 when it is not.
Bit 6 FAULT is 1 when the printer is in the fault state and 0 when it is
not.
