VMIVME-7807自動化卡件，GE使用方法教程
位設(shè)置和清除指令不應(yīng)用于此控制寄存器。因為中斷被將1寫入狀態(tài)位，狀態(tài)位為1至指示掛起的中斷，讀-修改-寫序列可能清除掛起的中斷。這些位對滴答定時器生成的中斷電平進行編程。這些位編程打印機生成的中斷級別。級別0不生成中斷。這些位通過重置。位3當(dāng)該位為高位時，中斷被啟用。中斷是此位低時禁用。該位通過重置清除。
VMIVME-7807自動化卡件位4當(dāng)該位較低時，ACK*的上升沿生成一個打斷當(dāng)該位較高時，ACK的下降沿*生成中斷。該位通過重置清除。位5當(dāng)中斷被啟用時，該位由上升或由第4位選擇的ACK*下降沿。這個鉆頭是邊緣敏感，通過向其寫入1或在打印機時清除中斷被禁用。位6當(dāng)中斷被啟用時，該位由故障*。該位對邊緣敏感，通過寫入1清除或當(dāng)打印機中斷被禁用時。位7當(dāng)該位高時，打印機中斷在以位0-2編程的電平。該位是位5和的或6、該位通過復(fù)位清除。由于級別0不生成中斷，因此該級別為用于輪詢軟件。這些位通過重置清除。位3當(dāng)該位為高位時，中斷被啟用。中斷是此位低時禁用。該位通過重置清除。位7當(dāng)該位為高位時，在以位0-2編程的電平。該位是邊緣敏感的，并且當(dāng)中斷發(fā)生時，由計時計時器執(zhí)行設(shè)置啟用。當(dāng)向其寫入1或當(dāng)中斷被禁用。清除后，它將保持清除狀態(tài)，直到下一步執(zhí)行。該位通過重置清除。
Bit set and clear instructions should not be used on this
control register. Because the interrupt is cleared by
writing a 1 to the status bit and the status bit is a 1 to
indicate a pending interrupt, the read-modify-write
sequence may clear a pending interrupt. These bits program the interrupt level the tick timer generates.These bits program the interrupt level the printer generates.
Level 0 does not generate an interrupt. These bits are cleared by
reset.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 4 When this bit is low, the rising edge of ACK* generates an
interrupt. When this bit is high, the falling edge of ACK*
generates an interrupt. This bit is cleared by reset.
Bit 5 When interrupts are enabled, this bit is set by the rising or
falling edge of ACK* as selected by bit 4. This bit is edge
sensitive and is cleared by writing a 1 to it or when printer
interrupts are disabled.
Bit 6 When interrupts are enabled, this bit is set by the falling edge of
FAULT*. This bit is edge sensitive and is cleared by writing a 1
to it or when printer interrupts are disabled.
Bit 7 When this bit is high, a printer interrupt is being generated at
the level programmed in bits 0-2. This bit is the OR of bits 5 and
6. This bit is cleared by reset.
Because level 0 does not generate an interrupt, this level is
intended for polling software. These bits are cleared by reset.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 7 When this bit is high, a tick timer interrupt is being generated at
the level programmed in bits 0-2. This bit is edge sensitive and it
is set by a carry out of the tick timer when interrupts are
enabled. This bit is cleared when a 1 is written to it or when the
interrupt is disabled. When cleared, it remains cleared until the
next carry out. This bit is cleared by reset.
