HONEYWELL LCNP4E 51405098-100卡件
本地總線超時每當MPU或PCC出現時，就會發生本地總線超時（LBTO）訪問（VMEbus范圍外）未在編程時間。如果系統配置正確，則應僅當軟件訪問車載地址范圍。每當LBTO發生時，LBTO狀態位在VMEchip中設置。VMEbus訪問超時每當PCC或MC68030 VMEbus綁定周期未接收VMEbus總線在編程時間內授予。這通常是由于另一個總線主控器長時間握住總線。當VATO發生時，VATO狀態位在VMEchip中設置。
HONEYWELL LCNP4E 51405098-100卡件VMEbus BERR公司*當BERR*信號線激活時，VMEbus BERR*發生當MC68030或PCC是VMEbus主機時。VMEbus BERR*僅在以下情況下發生：? 初始化例程采樣以查看是否存在設備在VMEbus上，它不是。? 壞軟件訪問VMEbus范圍。? 錯誤配置試圖訪問VMEbus上的設備錯誤（例如將LWORD*低電平驅動到16位板）。
? VMEbus上發生硬件錯誤。? VMEbus從機報告訪問錯誤（例如奇偶校驗錯誤）。
? 每當VMEbus BERR*發生時，VMEbus BERR*狀態位在VMEchip中設置。
本地RAM奇偶校驗錯誤當啟用奇偶校驗時，當前總線主機接收到如果正在訪問本地總線，則總線錯誤（或沒有LANRDY*，如果LANCE）出現DRAM和奇偶校驗錯誤。如果MC68030是本地總線主機發生奇偶校驗錯誤時，奇偶校驗錯誤（PE）狀態位在PCC狀態寄存器中設置。注意，該位僅在以下情況下有用：設置模式3奇偶校驗。如果設置了模式2奇偶校驗，則發生奇偶校驗后，MC68030無法讀取狀態
Local Bus Time-Out
A Local Bus Time-Out (LBTO) occurs whenever an MPU or PCC
access (outside of the VMEbus range) does not complete within the
programmed time. If the system is configured properly, this should
only happen if software accesses a nonexistent location within the
onboard address range. Whenever an LBTO occurs, the LBTO
status bit is set in the VMEchip.
VMEbus Access Time-Out
A VMEbus Access Time-Out (VATO) occurs whenever a PCC or
MC68030 VMEbus bound cycle does not receive a VMEbus Bus
Grant within the programmed time. This is usually caused by
another bus master holding the bus for an excessive period of time.
When a VATO occurs, the VATO status bit is set in the VMEchip.
VMEbus BERR*
The VMEbus BERR* occurs when the BERR* signal line is activated
on the VMEbus while the MC68030 or PCC is the VMEbus master.
VMEbus BERR* should occur only if:
? An initialization routine samples to see if a device is present
on the VMEbus and it is not.
? Bad software accesses a nonexistent device within the
VMEbus range.
? Bad configuration tries to access a device on the VMEbus
incorrectly (such as driving LWORD* low to a 16-bit board).
? A hardware error occurs on the VMEbus. ? A VMEbus slave reports an access error (such as parity error).
? Whenever a VMEbus BERR* occurs, the VMEbus BERR*
status bit is set in the VMEchip.
Local RAM Parity Error
When parity checking is enabled, the current bus master receives a
bus error (or no LANRDY*, if LANCE) if it is accessing the local
DRAM and a parity error occurs. If the MC68030 is the local bus
master when the parity error occurs, the Parity Error (PE) status bit
is set in the PCC status register. Note that this bit is only useful if
mode 3 parity checking is set. If mode 2 parity checking is set, the
MC68030 is not able to read status after the occurrence of the parity
error.
