PCD230A 3BHE022291R0101控制卡件,ABB配置教程
RWD位允許軟件配置請求者版本模式設置位時，如果RNEVER和DWB都是清除為0時，請求者在MC68030完成VMEbus循環。當位被清除時，如果RNEVER和DWB都被清除為0，請求者操作在請求發布（ROR）模式下。獲得控制權后在VMEbus中，它保持控制，直到檢測到另一個請求在VMEbus上掛起。該位通過任何重置清除。位5 RONR位控制VMEchip的方式請求VMEbus。當設置位時；任何時候MVME147擁有總線主控權
PCD230A 3BHE022291R0101控制卡件，然后放棄了VMEchip在檢測到總線之前，不會再次請求VMEbus請求信號BR*在其電平上被否定至少150納秒。當VMEchip檢測到BR*否定時，它會抑制再次駕駛至少200 ns。該位通過任何重置清除。位6當MVME147為VMEbus主機時，DHB狀態位為1否則為0。位7將DWB控制位設置為1會導致VMEchip請求
VMEbus（如果還沒有總線主控）。當VMEbus主控權已經獲得，直到之后才放棄DWB和RNEVER位均被清除。此位已清除通過任何重置。設置MASD16位迫使MVME147僅執行VMEbus上的D8和D16數據傳輸。清除MASD16位允許在當MC68030在以下范圍內訪問時的VMEbus$F0000000。（對高于$F0000000的VMEbus位置的訪問是無論MASD16位如何，始終限制為D8/D16。）該位由SYSRESET清除。位1，如果設置了MASA24位，或MC68030訪問VMEbus在低于1000000美元的范圍內，主驅動器驅動其中一個VMEbus期間的標準（24位）地址修飾符代碼周期（除非主機配置為使用主機地址主地址修飾符中描述的修飾符寄存器本章注冊部分）。具體標準AM代碼由MC68030在循環期間的三個功能代碼行，如表所示在下面該位由SYSRESET清除。位2，如果設置了MASA16位，或MC68030訪問高于$FFFF0000的VMEbus，短（16位）AM無論MASA24位的狀態如何（除非主機配置為使用主機地址修飾符寄存器如主地址修改器寄存器中所述本章第節）。具體的短AM代碼為根據MC68030在循環期間有三個功能代碼行，如下表。該位由SYSRESET清除。
The RWD bit allows software to configure the requester release
mode. When the bit is set, if RNEVER and DWB are both
cleared to 0, the requester releases the VMEbus after the
MC68030 completes a VMEbus cycle. When the bit is cleared, if
RNEVER and DWB are both cleared to 0, the requester operates
in the Release-On-Request (ROR) mode. After acquiring control
of the VMEbus, it maintains control until it detects another
request pending on the VMEbus. This bit is cleared by any reset.
Bit 5 The RONR bit controls the manner in which the VMEchip
requests the VMEbus. When the bit is set; anytime the
MVME147 has bus mastership, then gives it up, the VMEchip
does not request the VMEbus again until it detects the bus
request signal BR*, on its level, negated for at least 150 ns.
When the VMEchip detects BR* negated, it refrains from
driving it again for at least 200 ns.
This bit is cleared by any reset.
Bit 6 The DHB status bit is 1 when the MVME147 is VMEbus master
and 0 when it is not.
Bit 7 Setting the DWB control bit to 1 causes the VMEchip to request
the VMEbus (if not already bus master). When VMEbus
mastership has been obtained, it is not relinquished until after
the DWB and RNEVER bits are both cleared. This bit is cleared
by any reset.Setting the MASD16 bit forces the MVME147 to perform only
D8 and D16 data transfers on the VMEbus. Clearing the
MASD16 bit allows D8, D16, and D32 transfer capability on the
VMEbus when the MC68030 accesses in the range below
$F0000000. (Accesses to VMEbus locations above $F0000000 are
always restricted to D8/D16 regardless of the MASD16 bit.)
This bit is cleared by SYSRESET.
Bit 1 If either the MASA24 bit is set, or the MC68030 accesses the
VMEbus in the range below $1000000, the master drives one of
the standard (24-bit) address modifier codes during VMEbus
cycles (unless the master is configured to use the master address
modifier register as described in the Master Address Modifier
Register section in this chapter). The specific standard AM code
is determined from the levels that the MC68030 drives on the
three function code lines during the cycle, as shown in the table
below. This bit is cleared by SYSRESET.
