AMAT 0100-20001系統電子接口 PCB
1.產 品 資 料 介 紹：
中文資料：
AMAT 0100-20001規范沒有指定多字節傳輸的哪個字節最重要。然而，AMAT 0100-20001規范確實要求某些字節通道與某些字節地址相關聯。如第31頁表1-1所示，在L字傳輸期間，字節（0）必須在數據線D31-D24上傳輸，而字節（3）必須在線D7-D0上傳輸。這種字節和地址對齊與諸如Motorola 68040之類的Big Endian處理器完全相同。
如果Little Endian設備的數據總線直接連接到AMAT 0100-20001（即D31到D31、D30到D30等），那么在L字寫入期間提供給AMAT 0100-20001 D31-D24字節通道的最高有效字節數據將由AMAT 0100-20001存儲在四個目的地字節地址中的最低地址中——與Pentium微處理器預期的相反。
如果寫入的32位值總是使用類似的L字傳輸（即一次讀取所有四個字節）進行讀取，則這不會帶來問題，因為交換的數據會再次交換，并在主機上完全顯示。然而，如果要使用任何其他方法檢索由32位L字傳輸寫入的數據，例如，使用四個單獨的字節傳輸會產生問題。最低字節地址的數據會被錯誤地認為是最低有效的，而實際上它是最高有效的。
英文資料：
The AMAT 0100-20001 Specification does not specify which byte of a multiple-byte transfer is most significant. The AMAT 0100-20001 Specification does, however, require certain byte lanes to be associated with certain byte addresses. As shown in Table 1-1 on page 31, byte(0) must be transferred on data lines D31-D24 during a Lword transfer while byte(3) must be transferred on lines D7-D0. This byte and address alignment is exactly the same as that for a Big Endian processor such as the Motorola 68040.
If a Little Endian device were to have its data bus directly connected to the AMAT 0100-20001 (i.e., D31 to D31, D30 to D30, etc.), then the most significant byte data supplied to the AMAT 0100-20001 D31-D24 byte lane during a Lword write would be stored by the VAMAT 0100-20001in the lowest of the four destination byte addresses – opposite that expected by the Pentium microprocessor.
This poses no problem if the 32-bit value written is always read back using a similar Lword transfer (i.e., all four bytes at once), since the swapped data gets swapped again and appears to the Host exactly as it should. However, if the data written by the 32-bit Lword transfer were to be retrieved using any other method, for example, using four separate byte transfers creates a problem. The data at the lowest byte address would be incorrectly assumed to be the least significant, while it is actually the most significant.
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