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INTELLIX MO150變壓監(jiān)測器
設(shè)置從屬映像時(shí)，地址和其他參數(shù)應(yīng)首先設(shè)置。只有正確設(shè)置VMEbus從屬映像后，才應(yīng)：將啟用VMEbus從映像。如果要重新映射從屬映像，請先禁用從屬映像，然后重置地址。之后映像配置正確，請重新啟用映像。VMEbus從循環(huán)成為PCI總線上的主循環(huán)。PCI總線仲裁器是Intel 82443BX芯片。它在各種PCI主機(jī)、CPU和PCI總線是IDE總線主控控制器。由于無法重試VMEbus，因此必須允許處理所有VMEbus從屬周期。當(dāng)PCI循環(huán)到PCI從映像正在進(jìn)行，而VMEbus從映像循環(huán)到板載DRAM正在進(jìn)行中。PCI周期不會放棄PCI總線和VMEbus從設(shè)備循環(huán)不會放棄VMEbus，導(dǎo)致XVME-660死鎖。如果XVME-660將同時(shí)用作主設(shè)備和從設(shè)備，VMEbus主設(shè)備在啟動VMEbus循環(huán)之前，循環(huán)必須獲得VMEbus。
所有VMEbus從接口周期都進(jìn)行字節(jié)交換，以保持地址一致性。對于有關(guān)Xycom自動化軟件、可選字節(jié)交換硬件的更多信息關(guān)于XVME-660，請參閱第74頁。
VMEbus中斷處理
XVME-660可以服務(wù)于VME IRQ[7:1]。宇宙芯片中的寄存器啟用
XVME-660將服務(wù)的中斷級別。當(dāng)斷言VMEbus IRQ時(shí)，宇宙請求VMEbus并生成IACK循環(huán)。一旦IACK
循環(huán)完成后，生成PCI總線中斷，以允許正確的中斷服務(wù)
要執(zhí)行的例程（ISR）。盡管Universe連接到所有四個(gè)PCI總線中斷，但為了保持單功能設(shè)備的PCI兼容性，僅使用PIRQA。其他PCI總線設(shè)備可以共享這些中斷。BIOS映射宇宙PCI總線中斷到IRQ9上的AT總線中斷控制器。由于PCI設(shè)備共享中斷線，所有ISR例程必須準(zhǔn)備好鏈中斷向量以允許服務(wù)其他設(shè)備。
VMEbus中斷生成
XVME-660可以在所有七個(gè)級別上生成VMEbus中斷。有一個(gè)獨(dú)特的與每個(gè)級別關(guān)聯(lián)的狀態(tài)/ID。高位在狀態(tài)/ID中編程登記如果中斷源是軟件中斷，則清除最低位，并且為所有其他中斷源設(shè)置。有關(guān)更深入的解釋，請參閱《宇宙手冊》。VMEbus重置選項(xiàng)當(dāng)切換前面板復(fù)位開關(guān)時(shí)，XVME-660可執(zhí)行以下操作
重置選項(xiàng)：
1.僅重置VME背板。
2.僅重置XVME-660 CPU。
3.重置兩者。
4.重置兩者。
有關(guān)如何配置重置選項(xiàng)的信息，請參閱第14頁的開關(guān)設(shè)置。
When setting up slave images, the address and other parameters should
be set first. Only after the VMEbus slave image is set up correctly should
the VMEbus slave image be enabled. If a slave image is going to be remapped, disable the slave image first, and then reset the address. After
the image is configured correctly, re-enable the image.
The VMEbus slave cycle becomes a master cycle on the PCI bus. The PCI bus arbiter is
the Intel 82443BX chip. It arbitrates between the various PCI masters, the CPU, and the
PCI bus IDE bus mastering controller. Because the VMEbus cannot be retried, all VMEbus slave cycles must be allowed to be processed. This becomes a problem when a PCI
cycle to a PCI slave image is in progress while a VMEbus slave cycle to the onboard
DRAM is in progress. The PCI cycle will not give up the PCI bus and the VMEbus slave
cycle will not give up the VMEbus, causing the XVME-660 to become deadlocked. If the
XVME-660 is to be used as a master and a slave at the same time, the VMEbus master
cycles must obtain the VMEbus prior to initiating VMEbus cycles.
All VMEbus slave interface cycles are byte-swapped to maintain address coherency. For
more information on the Xycom Automation software selectable byte-swapping hardware
on the XVME-660, refer to p. 74.
VMEbus Interrupt Handling
The XVME-660 can service VME IRQ[7:1]. A register in the Universe chip enables the
interrupt levels that will be serviced by the XVME-660. When a VMEbus IRQ is asserted, the Universe requests the VMEbus and generates an IACK cycle. Once the IACK
cycle is complete, a PCI bus interrupt is generated to allow the proper Interrupt Service
Routine (ISR) to be executed. Although, the Universe connects to all four PCI bus interrupts, only PIRQA is used in order to maintain PCI compatibility for single-function devices. Other PCI bus devices may share these interrupts. The BIOS maps the Universe
PCI bus interrupts to the AT-bus interrupt controller on IRQ9.
Because the PCI devices share interrupt lines, all ISR routines must be prepared to chain
the interrupt vector to allow the other devices to be serviced.
VMEbus Interrupt Generation
The XVME-660 can generate VMEbus interrupts on all seven levels. There is a unique
STATUS/ID associated with each level. Upper bits are programmed in the STATUS/ID
register. The lowest bit is cleared if the source of the interrupt is a software interrupt, and
set for all other interrupt sources. Consult the Universe manual for a more in-depth explanation.VMEbus Reset Options
When the front panel Reset switch is toggled, the XVME-660 can perform the following
reset options:
1. Reset the VME backplane only.
2. Reset the XVME-660 CPU only.
3. Reset both.
4. Reset neither.
See Switch Settings on p. 14 for information on how to configure the Reset options.
