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Honeywell SPS5710-2-LF工控模塊
CRU320現在支持PACSystems RX3i熱網絡中的255個PROFINET I/O設備備用CPU冗余系統。PROFINET操作使用PROFINET I/O控制器模塊IC695PNC001。冗余操作符合PROFINET V2.3S-2型系統冗余。
中描述了HSB CPU冗余系統中的PROFINET I/O操作
以下用戶手冊：
? PACSystems熱備CPU冗余用戶手冊，GFK-2308K
? PACSystems RX3i PROFINET IO控制器用戶手冊，GFK-2571D增加了對IC695RMX228 128 MB反射式內存模塊的支持收發器。
增加了讀取IC695CMX128、IC695RMX128和IC695MMX128的反射存儲器狀態位的能力，以及IC695RMX228（反射存儲器模塊）。解決串行I/O讀取字節COMMREQ（4402）始終返回錯誤的問題發生錯誤時的代碼100Dh，無論錯誤如何。當CPU首次通電時，RS-485端口（COM 2）與變送器一起通電啟用。一旦CPU OK LED亮起，變送器將進入高阻抗狀態照亮。由于這需要有限的時間，如果COM 2端口是用于多點通信，其他設備通過wiredOR連接共享同一電纜。如果其中一個設備在CPU通電時正在進行通信上，這些通信有可能中斷，直到CPU將RS-485端口進入高阻抗狀態。在以前的版本中，CPU允許配置位內存中的COMMREQ狀態字非字節對齊邊界上的類型。即使給定的引用沒有被字節對齊，固件也會在更新狀態之前將其調整到下一個最低字節邊界位，覆蓋對齊邊界和指定位置之間的位。
為確保應用程序按預期運行，3.50版要求配置位存儲器類型中的COMMREQ狀態字將進行字節對齊。例如，如果用戶指定的狀態位位置為%I3，CPU將狀態位位置與%I1對齊。版本3.50固件要求用戶指定適當的對齊地址（%I1），以確保所使用的位置適合其應用。請注意，實際參考位置未更改使用的，但現在為用戶明確說明。PACSystems CPU接收來自多個系統的在停止和運行模式之間切換的請求不同的來源。這些包括（但不限于）Proficy機器版、HMI、用戶以及運行/停止開關。因為模式有許多潛在的來源
更改請求，可以接收新的模式更改請求
而另一個模式更改請求已經正在進行中。發生這種情況時，CPU評估新模式更改的優先級請求正在進行的模式更改。如果新模式更改請求具有與正在進行的優先級相等或更高，CPU將轉換到新的模式，而不是正在進行的模式。但是，如果新模式更改請求具有較低的優先級高于正在進行的優先級，新模式請求被丟棄，CPU完成正在進行的模式更改。掃描模式優先級為（從最高到最低優先級）：停止-停止、停止故障、停止和運行。（注意：IO啟用/禁用狀態不是模式優先級評估的一部分。）例如，CPU已啟用運行IO模式，執行服務請求13功能塊，將CPU置于停止IO禁用模式。在完成到停止IO禁用的轉換之前，運行/停止開關從啟用運行IO更改為禁用運行IO。在這種情況下，CPU忽略來自運行/停止開關的新請求進入運行IO禁用模式，因為：已在處理轉到停止IO禁用模式的請求，而停止模式具有更高的值優先于運行模式。
The CRU320 now supports 255 PROFINET I/O Devices in a PACSystems RX3i Hot
Standby CPU Redundancy system. PROFINET operation uses the PROFINET I/O
Controller module IC695PNC001. Redundant operation conforms to PROFINET V2.3
Type S-2 System Redundancy.
PROFINET I/O operation in a HSB CPU Redundancy system is described in the
following user manuals:
? PACSystems Hot Standby CPU Redundancy User’s Manual, GFK-2308K
? PACSystems RX3i PROFINET IO Controller User Manual, GFK-2571D Adds support for IC695RMX228 128 MB Reflective Memory Module with Single Mode
Transceiver.
Adds ability to read reflective memory status bits for IC695CMX128, IC695RMX128,
and IC695RMX228 (reflective memory modules).
Resolves issue of Serial I/O Read Bytes COMMREQ (4402) always returning error
code 100Dh in the event of an error, regardless of the error.When the CPU is first powered on, the RS-485 port (COM 2) powers up with the transmitter
enabled. The transmitter is placed into a high-impedance state once the CPU OK LED is
illuminated. Since that takes a finite amount of time, this could be an issue if the COM 2 port is
being used in multi-drop communications, and other devices share the same cable via wiredOR connections. If one of those devices is actively communicating when the CPU is powered
up, there is a potential for those communications to be disrupted until the CPU puts the
RS-485 port into high-impedance state.In previous releases, the CPU allowed configuration of COMMREQ Status Words in bit memory
types on a non-byte-aligned boundary. Even though the given reference was not bytealigned, the firmware would adjust it the next-lowest byte boundary before updating status
bits, overwriting the bits between the alignment boundary and specified location.
To ensure that the application operates as expected, release 3.50 requires configuration of
COMMREQ Status Words in bit memory types to be byte-aligned. For example if the user
specified status bit location of %I3, the CPU aligns the status bit location at %I1. Release 3.50
firmware requires the user to specify the appropriate aligned address (%I1) to ensure that the
utilized location is appropriate for their application. Note that the actual reference location
utilized is not changed, but now is explicitly stated for the user.The PACSystems CPU receives requests to change between STOP and RUN mode from many
different sources. These include (but are not limited to) Proficy Machine Edition, HMIs, the user
application, and the RUN/STOP switch. Since there are many potential sources for a mode
change request, it is possible to receive a new mode change request while another is already
in progress. When this occurs, the CPU evaluates the priority of the new mode change
request with the mode change that is in progress. If the new mode change request has an
equal or higher priority than the one already in progress, the CPU transitions to the new
mode instead of the one in progress. If, however, the new mode change request has a lower
priority than the one in progress, the new mode request is discarded and the CPU completes
the mode change that is in progress. The sweep mode priorities are (listed from highest to
lowest priority): STOP HALT, STOP FAULT, STOP, and RUN. (Note: The IO ENABLED/DISABLED
state is not part of the mode priority evaluation.) For example, a CPU is in RUN IO ENABLED
mode and a Service Request 13 function block is executed to place the CPU into STOP IO
DISABLED mode. Before the transition to STOP IO DISABLED is completed, the RUN/STOP
switch is changed from RUN IO ENABLED to RUN IO DISABLED. In this case, the CPU ignores
the new request from the RUN/STOP switch to go to RUN IO DISABLED mode because it is
already processing a request to go to STOP IO DISABLED mode and STOP mode has a higher
priority than RUN mode.
