HONEYWELL FTA-T-21使用參數(shù),FTA-T-21卡件
三組VMEbus信號控制與電路板的通信。具體如下：a、 數(shù)據(jù)總線D00至D15
b、 地址行A01、A02、A03、A04、A05、A06、A07c、 總線控制信號：
（1） 寫入（2） DS0，*DS1*（3） 系統(tǒng)時鐘（4） 系統(tǒng)重置*
數(shù)據(jù)總線是雙向的，可以在電路板之間移動數(shù)據(jù)通過16位數(shù)據(jù)收發(fā)器響應(yīng)來自控制的控制信號解碼器。數(shù)據(jù)收發(fā)器用作內(nèi)部數(shù)據(jù)總線的緩沖器，該總線互連板上的所有數(shù)據(jù)設(shè)備。
HONEYWELL FTA-T-21使用參數(shù)地址線A01到A07映射128個通信寄存器在VME地址空間內(nèi)的256字節(jié)范圍內(nèi)（第4節(jié)）。控制信號確定數(shù)據(jù)是移動到VMIVME-3112（寫入）還是從VMIVME-3112（讀取）提供必要的數(shù)據(jù)選通（DS0、DS1）和提供16 MHz時鐘（SYS CLK），供車載計時器使用。系統(tǒng)復(fù)位輸入重置所有計時器和標志。靜態(tài)控件鎖存在控制寄存器中并使用主要是建立董事會的運作模式。必要的狀態(tài)標志用于監(jiān)測和控制模擬輸入多路復(fù)用器和ADC通過狀態(tài)寄存器。參考控制和狀態(tài)寄存器統(tǒng)稱為控制和狀態(tài)寄存器（CSR），因為它們位于同一位置住址寫入信號決定訪問哪一個。大部分控件可以通過狀態(tài)寄存器直接監(jiān)控寄存器輸出。3.4模數(shù)轉(zhuǎn)換器（ADC）控制和定時與控制ADC相關(guān)的控制命令和狀態(tài)標志如圖3.3-1所示，并在第4節(jié)和以下章節(jié)中進行了描述。CSR中有三個模式控制位。這些程序的編程控制位（模式0H到模式2H）確定五個ADC中的哪一個電路板操作模式。五種ADC工作模式和控制寄存器模式控制位是ADC操作模式，基本上決定了板載ADC和通道選擇由CPU板或板載外部控制通道定序器。它們還確定是否將生成中斷轉(zhuǎn)換完成時。五種ADC操作模式為第4節(jié)從編程的角度進行了描述。自動掃描模式（模式0）、隨機輪詢模式和這里將討論掃描輪詢模式，以揭示ADC控制和定時間隔。其他兩種模式使用中斷而不是輪詢來確定當一個轉(zhuǎn)換或一系列轉(zhuǎn)換完成時
After board-selection has occurred, three groups of VMEbus signals
control communications with the board. They are as follows:
a. Data Bus lines D00 to D15
b. Address lines A01, A02, A03, A04, A05, A06, A07
c. Bus Control Signals:
(1) WRITE
(2) DS0,* DS1*
(3) SYS CLK
(4) SYS RESET*
Data bus lines are bi-directional and move data to and from the board
through a 16-bit data transceiver in response to control signals from the control
decoder. The data transceiver serves as a buffer for the internal data bus which
interconnects all data devices on the board.
Address lines A01 through A07 map the 128 communication registers
onto a 256-byte range within the VME address space (Section 4). The control
signals determine whether data is to be moved to the VMIVME-3112 (write) or from
the VMIVME-3112 (read), provide the necessary data strobes (DS0, DS1), and
supply a 16 MHz clock (SYS CLK) for use by on-board timers. A SYS RESET input
resets all timers and flags.
Static controls are latched into the Control Register and are used
primarily to establish the operational mode of the board. Status flags, necessary
for monitoring and controlling the analog input multiplexer and the ADC are read
through the Status Register. The control and status registers are referred to
collectively as the Control and Status Register (CSR), since they are at the same
address. The WRITE signal determines which one is accessed. Most of the control
register outputs can be monitored directly through the Status Register.
3.4 ANALOG-TO-DIGITAL (ADC) CONTROL AND TIMING
Control commands and status flags associated with controlling the ADC
are illustrated in Figure 3.3-1, and are described in Section 4 and the following sections.
There are three mode control bits in the CSR. The programming of these
control bits (Mode 0H through Mode 2H) determine which one of five ADC
operating modes the board is to operate in. The five ADC operating modes and the
Control Register mode control bits areThe ADC operating modes basically determine if the on-board ADC and
channel selection are controlled externally by a CPU board or by the on-board
channel sequencer. They also determine whether an interrupt will be generated
when the conversion(s) are complete. The five ADC operating modes will be
described from a programming viewpoint in Section 4.
The AUTO SCANNING MODE (Mode 0), RANDOM POLL MODES, and
SCANNING POLL MODE will be discussed here to reveal the ADC controls and
timing intervals. The other two modes use interrupts instead of polling to determine
when a conversion or a series of conversions are completed.
